The present invention generally relates to clock generator circuits. More particularly, the present invention relates to clock generator circuits for providing stable clock signals and double frequency clock signals in memory devices. The clock generator circuits in accordance with the present invention may serve as an oscillator or a frequency doubler.
Clock circuits play an important role in modern electronic products. Generally, a clock signal generated by a clock circuit within an integrated circuit or on a printed circuit board of an electronic device is used for signal synchronization in the electronic device. Moreover, a clock circuit may generate clock signals at different clock rates for applications requiring different operation frequencies. The clock signals of different clock rates may be generated by multiplying or dividing the frequency of a reference clock signal.
A clock signal may be generated by a resistance-capacitance (RC) delay circuit. FIG. 1 is a circuit diagram of an RC delay clock generator 10 in prior art. Referring to FIG. 1, the RC delay clock generator 10 may include resistors R1 and R2 and capacitors C1 and C2, wherein R1 and C1 form a first RC delay circuit and R2 and C2 form a second RC delay circuit. Under the control of a clock enable signal Clken, an output clock signal Clkout of the clock generator 10 may be generated. The output clock signal Clkout has a period T1 equal to R1C1+R2C2. However, the clock generator 10 may be susceptible to variations in supply voltage VDD and temperature, which may cause deviations in the time constants R1C1 and R2C2, resulting in an unstable and unreliable output clock signal Clkout.
To address the issue, a clock circuit substantially free from the VDD and temperature variations has been proposed. FIG. 2 is a circuit diagram of a clock generator 20 in prior art. Referring to FIG. 2, the clock generator 20 may include a bandgap circuit 21 and a constant current generator 22. The bandgap circuit 21 may generate a reference current IREF and a reference voltage VREF. The current generator 22 may generate a bias voltage Vbias, which may cause the generation of a mirror current ICONST based on the reference current IREF. Under the control of a clock enable signal Clken, an output clock signal Clkout has a period T2 equal to 2C (VREF/ICONST), where “C” represents the capacitance of capacitors C3 and C4 in the clock generator 20. Although the clock generator 20 may provide a more stable and reliable output clock signal than the clock generator 10 illustrated in FIG. 1, the bandgap circuit 21 may be so complicated as to render the clock generator 20 cost ineffective or chip area inefficient in some applications. Moreover, the setup time of the bandgap circuit 21, on the order of several microseconds (us), may not be acceptable in certain applications.
Like the clock generators, frequency multipliers and dividers may also suffer VDD and temperature variations. FIG. 3A is a circuit diagram of a frequency multiplier 30 in prior art. Referring to FIG. 3A, the frequency multiplier 30 includes an RC delay one-shot pulse circuit, which generates an output clock signal Clkout in response to external clock signals Clkext. FIG. 3B is a diagram illustrating the waveforms of the external clock signals Clkext, the output clock signal Clkout and the signals at points “a” and “b” in FIG. 3A. Given a 50% duty cycle, the pulse widths of the signals at points “a” and “b” may be significantly smaller (shown in solid lines) or greater (shown in dashed lines) than a desired one due to variations in VDD and temperature, resulting in deviations in the output clock signal Clkout. To address the issue, a phase lock loop (PLL) may be used to track and stabilize the duty cycle. However, PLL may cause other issues such as stability and design complexity.
It may therefore be desirable to have a clock generator that is able to alleviate the issue of VDD and temperature variations and may be designed in a relatively simple structure.